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33set -e
44
5- FLAGS= " --std=08 -fsynopsys -fexplicit -frelaxed "
5+ DIR=../resources/vhdl
66
7- ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink.vhdl
8- ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink_pkg.vhdl
9- ghdl -a $FLAGS ../resources/vhdl/top.vhdl
7+ FLAGS=" --std=08 -fsynopsys -fexplicit -frelaxed"
108
119GENERICS=" -gBOO=true -gINT=255 -gLOG='1' -gVEC=" 11111111" -gCHR='Z' -gSTR=" WXYZ" -gSKIP_REA=1"
12- ghdl --synth $FLAGS $GENERICS Top ARCH_SEL
10+
11+ # ##############################################################################
12+ # Alternative 1
13+ # ##############################################################################
14+
15+ # This alternative is better to specify particular options per file
16+
17+ ghdl -a $FLAGS --work=blink_lib $DIR /blink.vhdl
18+ ghdl -a $FLAGS --work=blink_lib $DIR /blink_pkg.vhdl
19+ ghdl -a $FLAGS $DIR /top.vhdl
20+
21+ # --out=raw-vhdl generate a VHDL 93 netlist
22+
23+ ghdl synth $FLAGS --out=raw-vhdl $GENERICS Top ARCH_SEL
24+
25+ # This alternative creates .cf files
26+
27+ rm -fr * .cf
28+
29+ # ##############################################################################
30+ # Alternative 2
31+ # ##############################################################################
32+
33+ # This alternative is more concise
34+
35+ # --work=<LIBNAME> applies to the following files
36+ # --out=verilog generate a Verilog netlist
37+
38+ ghdl synth $FLAGS --out=verilog $GENERICS \
39+ --work=blink_lib $DIR /blink.vhdl $DIR /blink_pkg.vhdl \
40+ --work=work $DIR /top.vhdl -e Top ARCH_SEL
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