Example output of ast_code_generator in README is updated.

Author: shtaxxx

README.md

@@ -348,17 +348,16 @@ python3 test.py
 Then Verilog HDL code generated from the AST instances is displayed.
 
 ```verilog
-
 module top
- (
-  input [0:0] CLK, 
-input [0:0] RST, 
-output [7:0] led
+(
+  input CLK,
+  input RST,
+  output [7:0] led
+);
 
- );
   assign led = 8;
-endmodule
 
+endmodule
 ```
 
 

README.rst

@@ -374,15 +374,15 @@ Then Verilog HDL code generated from the AST instances is displayed.
 
 .. code:: verilog
 
-
     module top
-     (
-      input [0:0] CLK, 
-    input [0:0] RST, 
-    output [7:0] led
+    (
+      input CLK,
+      input RST,
+      output [7:0] led
+    );
 
-     );
       assign led = 8;
+
     endmodule
 
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