Merge branch '1.1.4-rc'

Author: shtaxxx

pyverilog/vparser/ast.py

@@ -33,7 +33,7 @@ def show(self, buf=sys.stdout, offset=0, attrnames=False, showlineno=True):
         if self.attr_names:
             if attrnames:
                 nvlist = [(n, getattr(self, n)) for n in self.attr_names]
-                attrstr = ', '.join('%s=%s' & nv for nv in nvlist)
+                attrstr = ', '.join('%s=%s' % (n, v) for (n, v) in nvlist)
             else:
                 vlist = [getattr(self, n) for n in self.attr_names]
                 attrstr = ', '.join('%s' % v for v in vlist)
@@ -734,6 +734,14 @@ def children(self):
         return tuple(nodelist)
 
 
+class AlwaysFF(Always):
+    pass
+
+
+class AlwaysComb(Always):
+    pass
+
+
 class SensList(Node):
     attr_names = ()
 
@@ -875,6 +883,10 @@ class CasexStatement(CaseStatement):
     pass
 
 
+class UniqueCaseStatement(CaseStatement):
+    pass
+
+
 class Case(Node):
     attr_names = ()
 

pyverilog/vparser/lexer.py

@@ -53,10 +53,10 @@ def token(self):
     keywords = (
         'MODULE', 'ENDMODULE', 'BEGIN', 'END', 'GENERATE', 'ENDGENERATE', 'GENVAR',
         'FUNCTION', 'ENDFUNCTION', 'TASK', 'ENDTASK',
-        'INPUT', 'INOUT', 'OUTPUT', 'TRI', 'REG', 'WIRE', 'INTEGER', 'REAL', 'SIGNED',
+        'INPUT', 'INOUT', 'OUTPUT', 'TRI', 'REG', 'LOGIC', 'WIRE', 'INTEGER', 'REAL', 'SIGNED',
         'PARAMETER', 'LOCALPARAM', 'SUPPLY0', 'SUPPLY1',
-        'ASSIGN', 'ALWAYS', 'SENS_OR', 'POSEDGE', 'NEGEDGE', 'INITIAL',
-        'IF', 'ELSE', 'FOR', 'WHILE', 'CASE', 'CASEX', 'ENDCASE', 'DEFAULT',
+        'ASSIGN', 'ALWAYS', 'ALWAYS_FF', 'ALWAYS_COMB', 'SENS_OR', 'POSEDGE', 'NEGEDGE', 'INITIAL',
+        'IF', 'ELSE', 'FOR', 'WHILE', 'CASE', 'CASEX', 'UNIQUE', 'ENDCASE', 'DEFAULT',
         'WAIT', 'FOREVER', 'DISABLE', 'FORK', 'JOIN',
     )
 

pyverilog/vparser/parser.py

@@ -122,6 +122,7 @@ def p_moduledef(self, p):
         p[0] = ModuleDef(name=p[2], paramlist=p[3], portlist=p[4], items=p[5],
                          default_nettype=self.get_default_nettype(), lineno=p.lineno(1))
         p.set_lineno(0, p.lineno(1))
+        p[0].end_lineno = p.lineno(6)
 
     def p_modulename(self, p):
         'modulename : ID'
@@ -306,6 +307,11 @@ def p_sigtype_reg(self, p):
         p[0] = p[1]
         p.set_lineno(0, p.lineno(1))
 
+    def p_sigtype_logic(self, p):
+        'sigtype : LOGIC'
+        p[0] = p[1]
+        p.set_lineno(0, p.lineno(1))
+
     def p_sigtype_wire(self, p):
         'sigtype : WIRE'
         p[0] = p[1]
@@ -465,6 +471,8 @@ def p_standard_item(self, p):
         | genvardecl
         | assignment
         | always
+        | always_ff
+        | always_comb
         | initial
         | instance
         | function
@@ -1262,6 +1270,14 @@ def p_always(self, p):
         p[0] = Always(p[2], p[3], lineno=p.lineno(1))
         p.set_lineno(0, p.lineno(1))
 
+    def p_always_ff(self, p):
+        'always_ff : ALWAYS_FF senslist always_statement'
+        p[0] = AlwaysFF(p[2], p[3], lineno=p.lineno(1))
+
+    def p_always_comb(self, p):
+        'always_comb : ALWAYS_COMB senslist always_statement'
+        p[0] = AlwaysComb(p[2], p[3], lineno=p.lineno(1))
+
     def p_sens_egde_paren(self, p):
         'senslist : AT LPAREN edgesigs RPAREN'
         p[0] = SensList(p[3], lineno=p.lineno(1))
@@ -1364,6 +1380,7 @@ def p_basic_statement(self, p):
         """basic_statement : if_statement
         | case_statement
         | casex_statement
+        | unique_case_statement
         | for_statement
         | while_statement
         | event_statement
@@ -1606,6 +1623,12 @@ def p_casex_statement(self, p):
         p[0] = CasexStatement(p[3], p[5], lineno=p.lineno(1))
         p.set_lineno(0, p.lineno(1))
 
+    def p_unique_case_statement(self, p):
+        'unique_case_statement : UNIQUE CASE LPAREN case_comp RPAREN casecontent_statements ENDCASE'
+        p[0] = UniqueCaseStatement(p[3], p[5], lineno=p.lineno(1))
+        p.set_lineno(0, p.lineno(1))
+
+
     def p_case_comp(self, p):
         'case_comp : expression'
         p[0] = p[1]