@@ -123,7 +123,7 @@ static esp_err_t on_lowlevel_init_done(esp_eth_handle_t eth_handle){
123123 // gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_EMAC_TX_CLK);
124124 // PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[0]);
125125 pinMode (0 , INPUT);
126- pinMode ( 0 , FUNCTION_6 );
126+ PIN_FUNC_SELECT (GPIO_PIN_MUX_REG[ 0 ], 5 );
127127 EMAC_EXT.ex_clk_ctrl .ext_en = 1 ;
128128 EMAC_EXT.ex_clk_ctrl .int_en = 0 ;
129129 EMAC_EXT.ex_oscclk_conf .clk_sel = 1 ;
@@ -135,7 +135,7 @@ static esp_err_t on_lowlevel_init_done(esp_eth_handle_t eth_handle){
135135 // gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1);
136136 // PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[0]);
137137 pinMode (0 , OUTPUT);
138- pinMode ( 0 , FUNCTION_2 );
138+ PIN_FUNC_SELECT (GPIO_PIN_MUX_REG[ 0 ], 1 );
139139 // Choose the APLL clock to output on GPIO
140140 REG_WRITE (PIN_CTRL, 6 );
141141#endif
@@ -145,15 +145,15 @@ static esp_err_t on_lowlevel_init_done(esp_eth_handle_t eth_handle){
145145 // gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT);
146146 // PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[16]);
147147 pinMode (16 , OUTPUT);
148- pinMode ( 16 , FUNCTION_6 );
148+ PIN_FUNC_SELECT (GPIO_PIN_MUX_REG[ 16 ], 5 );
149149#endif
150150 } else if (eth_clock_mode == ETH_CLOCK_GPIO17_OUT){
151151#if CONFIG_ETH_RMII_CLK_OUT_GPIO != 17
152152 // RMII CLK (50MHz) output to GPIO17
153153 // gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, FUNC_GPIO17_EMAC_CLK_OUT_180);
154154 // PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[17]);
155155 pinMode (17 , OUTPUT);
156- pinMode ( 17 , FUNCTION_6 );
156+ PIN_FUNC_SELECT (GPIO_PIN_MUX_REG[ 17 ], 5 );
157157#endif
158158 }
159159#if CONFIG_ETH_RMII_CLK_INPUT
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