diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s
index 702b82223b36af..0979e7d4572888 100644
--- a/src/cmd/asm/internal/asm/testdata/riscv64.s
+++ b/src/cmd/asm/internal/asm/testdata/riscv64.s
@@ -244,6 +244,10 @@ start:
 	AMOMINUW	X5, (X6), X7			// af2353c6
 	AMOMINUD	X5, (X6), X7			// af3353c6
 
+	// 15: Wait-on-Reservation-Set Instructions (Zawrs)
+	WRSNTO                              // 7300d000
+	WRSSTO                              // 7300d001
+
 	// 20.5: Single-Precision Load and Store Instructions
 	FLW	(X5), F0				// 07a00200
 	FLW	4(X5), F0				// 07a04200
diff --git a/src/cmd/internal/obj/riscv/anames.go b/src/cmd/internal/obj/riscv/anames.go
index 6c48e2f7de4799..f925ac065334f8 100644
--- a/src/cmd/internal/obj/riscv/anames.go
+++ b/src/cmd/internal/obj/riscv/anames.go
@@ -98,6 +98,8 @@ var Anames = []string{
 	"AMOMAXUW",
 	"AMOMINW",
 	"AMOMINUW",
+	"WRSNTO",
+	"WRSSTO",
 	"FLW",
 	"FSW",
 	"FADDS",
diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go
index 60174a0b3a245f..8f283d4798c528 100644
--- a/src/cmd/internal/obj/riscv/cpu.go
+++ b/src/cmd/internal/obj/riscv/cpu.go
@@ -456,6 +456,10 @@ const (
 	AAMOMINW
 	AAMOMINUW
 
+	// 15: Wait-on-Reservation-Set Instructions (Zawrs)
+	AWRSNTO
+	AWRSSTO
+
 	// 20.5: Single-Precision Load and Store Instructions
 	AFLW
 	AFSW
diff --git a/src/cmd/internal/obj/riscv/inst.go b/src/cmd/internal/obj/riscv/inst.go
index a5b3acdb18110c..f1c61e891109c1 100644
--- a/src/cmd/internal/obj/riscv/inst.go
+++ b/src/cmd/internal/obj/riscv/inst.go
@@ -1,4 +1,4 @@
-// Code generated by ./parse.py -go rv64_a rv64_c rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_c rv_c_d rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbs rv_zicond rv_zicsr; DO NOT EDIT.
+// Code generated by ./parse.py -go rv64_a rv64_c rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_c rv_c_d rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zawrs rv_zba rv_zbb rv_zbs rv_zicond rv_zicsr; DO NOT EDIT.
 package riscv
 
 import "cmd/internal/obj"
@@ -1800,6 +1800,10 @@ func encode(a obj.As) *inst {
 		return &inst{0x57, 0x2, 0x2, 0x0, 1152, 0x24}
 	case AWFI:
 		return &inst{0x73, 0x0, 0x0, 0x5, 261, 0x8}
+	case AWRSNTO:
+		return &inst{0x73, 0x0, 0x0, 0xd, 13, 0x0}
+	case AWRSSTO:
+		return &inst{0x73, 0x0, 0x0, 0x1d, 29, 0x0}
 	case AXNOR:
 		return &inst{0x33, 0x4, 0x0, 0x0, 1024, 0x20}
 	case AXOR:
diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go
index e55c206a98e434..3badfaa5dd7029 100644
--- a/src/cmd/internal/obj/riscv/obj.go
+++ b/src/cmd/internal/obj/riscv/obj.go
@@ -2032,6 +2032,10 @@ var instructions = [ALAST & obj.AMask]instructionData{
 	AFLD & obj.AMask: {enc: iFEncoding},
 	AFSD & obj.AMask: {enc: sFEncoding},
 
+	// 15: Wait-on-Reservation-Set Instructions (Zawrs)
+	AWRSNTO & obj.AMask: {enc: iIIEncoding},
+	AWRSSTO & obj.AMask: {enc: iIIEncoding},
+
 	// 21.4: Double-Precision Floating-Point Computational Instructions
 	AFADDD & obj.AMask:   {enc: rFFFEncoding},
 	AFSUBD & obj.AMask:   {enc: rFFFEncoding},
@@ -3610,6 +3614,9 @@ func instructionsForProg(p *obj.Prog) []*instruction {
 		ins.funct7 = 3
 		ins.rd, ins.rs1, ins.rs2 = uint32(p.RegTo2), uint32(p.To.Reg), uint32(p.From.Reg)
 
+	case AWRSNTO, AWRSSTO:
+		ins.rd, ins.rs1 = REG_ZERO, REG_ZERO
+
 	case AECALL, AEBREAK:
 		insEnc := encode(p.As)
 		if p.To.Type == obj.TYPE_NONE {