diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s
index 702b82223b36af..e7ba78d3a5684f 100644
--- a/src/cmd/asm/internal/asm/testdata/riscv64.s
+++ b/src/cmd/asm/internal/asm/testdata/riscv64.s
@@ -195,11 +195,11 @@ start:
 	RDTIME		X5				// f32210c0
 	RDINSTRET	X5				// f32220c0
 
-	// 12.3: Integer Conditional Operations (Zicond)
-	CZEROEQZ	X5, X6, X7			// b353530e
-	CZEROEQZ	X5, X7				// b3d3530e
-	CZERONEZ	X5, X6, X7			// b373530e
-	CZERONEZ	X5, X7				// b3f3530e
+	// 9: Zihintntl Extension
+	NTLP1					// 33002000
+	NTLPALL					// 33003000
+	NTLS1					// 33004000
+	NTLALL					// 33005000
 
 	// 13.1: Multiplication Operations
 	MUL	X5, X6, X7				// b3035302
diff --git a/src/cmd/internal/obj/riscv/anames.go b/src/cmd/internal/obj/riscv/anames.go
index 6c48e2f7de4799..5146b5ad23df19 100644
--- a/src/cmd/internal/obj/riscv/anames.go
+++ b/src/cmd/internal/obj/riscv/anames.go
@@ -61,6 +61,10 @@ var Anames = []string{
 	"CSRRWI",
 	"CSRRSI",
 	"CSRRCI",
+	"NTLP1",
+	"NTLPALL",
+	"NTLS1",
+	"NTLALL",
 	"CZEROEQZ",
 	"CZERONEZ",
 	"MUL",
diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go
index 60174a0b3a245f..196b2eecc2e2cd 100644
--- a/src/cmd/internal/obj/riscv/cpu.go
+++ b/src/cmd/internal/obj/riscv/cpu.go
@@ -409,6 +409,12 @@ const (
 	ACSRRSI
 	ACSRRCI
 
+	// 9: Zihintntl Extension
+	ANTLP1
+	ANTLPALL
+	ANTLS1
+	ANTLALL
+
 	// 12.3: Integer Conditional Operations (Zicond)
 	ACZEROEQZ
 	ACZERONEZ
diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go
index e55c206a98e434..3df3da70aa7ff9 100644
--- a/src/cmd/internal/obj/riscv/obj.go
+++ b/src/cmd/internal/obj/riscv/obj.go
@@ -54,6 +54,26 @@ func jalToSym(ctxt *obj.Link, p *obj.Prog, lr int16) {
 // progedit is called individually for each *obj.Prog. It normalizes instruction
 // formats and eliminates as many pseudo-instructions as possible.
 func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) {
+	// Convert pseudo instructions into real riscv64 instructions.
+	switch p.As {
+	case ANTLP1, ANTLPALL, ANTLS1, ANTLALL:
+		switch p.As {
+		case ANTLP1:
+			p.From.Reg = REG_X2
+		case ANTLPALL:
+			p.From.Reg = REG_X3
+		case ANTLS1:
+			p.From.Reg = REG_X4
+		case ANTLALL:
+			p.From.Reg = REG_X5
+		}
+		p.As = AADD
+		p.From.Type = obj.TYPE_REG
+		p.Reg = REG_ZERO
+		p.To.Reg = REG_ZERO
+		p.To.Type = obj.TYPE_REG
+	}
+
 	insData, err := instructionDataForAs(p.As)
 	if err != nil {
 		panic(fmt.Sprintf("failed to lookup instruction data for %v: %v", p.As, err))