[CodeGen] Remove static member function Register::isPhysicalRegister. NFC

topperc · topperc · commit 5fadb3d68090 · 2025-02-20T10:49:53.000-08:00
Prefer the nonstatic member by converting unsigned to Register instead.
diff --git a/llvm/include/llvm/CodeGen/RDFRegisters.h b/llvm/include/llvm/CodeGen/RDFRegisters.h
@@ -111,7 +111,7 @@ struct RegisterRef {
   }
 
   static constexpr bool isRegId(unsigned Id) {
-    return Register::isPhysicalRegister(Id);
+    return Register(Id).isPhysical();
   }
   static constexpr bool isUnitId(unsigned Id) {
     return Register(Id).isVirtual();
diff --git a/llvm/include/llvm/CodeGen/Register.h b/llvm/include/llvm/CodeGen/Register.h
@@ -48,12 +48,6 @@ class Register {
     return Register(FI + MCRegister::FirstStackSlot);
   }
 
-  /// Return true if the specified register number is in
-  /// the physical register namespace.
-  static constexpr bool isPhysicalRegister(unsigned Reg) {
-    return MCRegister::isPhysicalRegister(Reg);
-  }
-
   /// Convert a 0-based index to a virtual register number.
   /// This is the inverse operation of VirtReg2IndexFunctor below.
   static Register index2VirtReg(unsigned Index) {
@@ -67,7 +61,9 @@ class Register {
 
   /// Return true if the specified register number is in the physical register
   /// namespace.
-  constexpr bool isPhysical() const { return isPhysicalRegister(Reg); }
+  constexpr bool isPhysical() const {
+    return MCRegister::isPhysicalRegister(Reg);
+  }
 
   /// Convert a virtual register number to a 0-based index. The first virtual
   /// register in a function will get the index 0.
diff --git a/llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp b/llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
@@ -525,7 +525,7 @@ void llvm::calculateDbgEntityHistory(const MachineFunction *MF,
           // Don't consider SP to be clobbered by register masks.
           for (auto It : RegVars) {
             unsigned int Reg = It.first;
-            if (Reg != SP && Register::isPhysicalRegister(Reg) &&
+            if (Reg != SP && Register(Reg).isPhysical() &&
                 MO.clobbersPhysReg(Reg))
               RegsToClobber.push_back(Reg);
           }
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
@@ -564,7 +564,7 @@ DIE &DwarfCompileUnit::updateSubprogramScopeDIE(const DISubprogram *SP,
         TFI->getDwarfFrameBase(*Asm->MF);
     switch (FrameBase.Kind) {
     case TargetFrameLowering::DwarfFrameBase::Register: {
-      if (Register::isPhysicalRegister(FrameBase.Location.Reg)) {
+      if (Register(FrameBase.Location.Reg).isPhysical()) {
         MachineLocation Location(FrameBase.Location.Reg);
         addAddress(*SPDie, dwarf::DW_AT_frame_base, Location);
       }
diff --git a/llvm/lib/CodeGen/LiveRangeCalc.cpp b/llvm/lib/CodeGen/LiveRangeCalc.cpp
@@ -216,7 +216,7 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
       report_fatal_error("Use not jointly dominated by defs.");
     }
 
-    if (Register::isPhysicalRegister(PhysReg)) {
+    if (Register(PhysReg).isPhysical()) {
       const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
       bool IsLiveIn = MBB->isLiveIn(PhysReg);
       for (MCRegAliasIterator Alias(PhysReg, TRI, false); !IsLiveIn && Alias.isValid(); ++Alias)
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -3966,8 +3966,7 @@ void GenericScheduler::reschedulePhysReg(SUnit *SU, bool isTop) {
   // Find already scheduled copies with a single physreg dependence and move
   // them just above the scheduled instruction.
   for (SDep &Dep : Deps) {
-    if (Dep.getKind() != SDep::Data ||
-        !Register::isPhysicalRegister(Dep.getReg()))
+    if (Dep.getKind() != SDep::Data || !Register(Dep.getReg()).isPhysical())
       continue;
     SUnit *DepSU = Dep.getSUnit();
     if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -708,7 +708,7 @@ void RegAllocFastImpl::reloadAtBegin(MachineBasicBlock &MBB) {
 /// not used by a virtreg. Kill the physreg, marking it free. This may add
 /// implicit kills to MO->getParent() and invalidate MO.
 bool RegAllocFastImpl::usePhysReg(MachineInstr &MI, MCPhysReg Reg) {
-  assert(Register::isPhysicalRegister(Reg) && "expected physreg");
+  assert(Register(Reg).isPhysical() && "expected physreg");
   bool displacedAny = displacePhysReg(MI, Reg);
   setPhysRegState(Reg, regPreAssigned);
   markRegUsedInInstr(Reg);
@@ -1289,7 +1289,7 @@ void RegAllocFastImpl::dumpState() const {
     assert(VirtReg.isVirtual() && "Bad map key");
     MCPhysReg PhysReg = LR.PhysReg;
     if (PhysReg != 0) {
-      assert(Register::isPhysicalRegister(PhysReg) && "mapped to physreg");
+      assert(Register(PhysReg).isPhysical() && "mapped to physreg");
       for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
         assert(RegUnitStates[Unit] == VirtReg && "inverse map valid");
       }
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -501,8 +501,8 @@ bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
             F.isClobberKind()) {
           // Check for def of register or earlyclobber register.
           for (; NumVals; --NumVals, ++i) {
-            unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
-            if (Register::isPhysicalRegister(Reg))
+            Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
+            if (Reg.isPhysical())
               CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
           }
         } else
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -10125,9 +10125,8 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
     auto DetectWriteToReservedRegister = [&]() {
       const MachineFunction &MF = DAG.getMachineFunction();
       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
-      for (unsigned Reg : OpInfo.AssignedRegs.Regs) {
-        if (Register::isPhysicalRegister(Reg) &&
-            TRI.isInlineAsmReadOnlyReg(MF, Reg)) {
+      for (Register Reg : OpInfo.AssignedRegs.Regs) {
+        if (Reg.isPhysical() && TRI.isInlineAsmReadOnlyReg(MF, Reg)) {
           const char *RegName = TRI.getName(Reg);
           emitInlineAsmError(Call, "write to reserved register '" +
                                        Twine(RegName) + "'");
@@ -11389,7 +11388,7 @@ void SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V,
   assert((Op.getOpcode() != ISD::CopyFromReg ||
           cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
          "Copy from a reg to the same reg!");
-  assert(!Register::isPhysicalRegister(Reg) && "Is a physreg");
+  assert(!Register(Reg).isPhysical() && "Is a physreg");
 
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   // If this is an InlineAsm we have to match the registers required, not the
diff --git a/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp b/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
@@ -155,11 +155,11 @@ bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd,
 
   LiveIntervals &LIs = G.getMetadata().LIS;
 
-  if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) {
-    LLVM_DEBUG(dbgs() << "Rd is a physical reg:"
-                      << Register::isPhysicalRegister(Rd) << '\n');
-    LLVM_DEBUG(dbgs() << "Ra is a physical reg:"
-                      << Register::isPhysicalRegister(Ra) << '\n');
+  if (Register(Rd).isPhysical() || Register(Ra).isPhysical()) {
+    LLVM_DEBUG(dbgs() << "Rd is a physical reg:" << Register(Rd).isPhysical()
+                      << '\n');
+    LLVM_DEBUG(dbgs() << "Ra is a physical reg:" << Register(Ra).isPhysical()
+                      << '\n');
     return false;
   }
 
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1108,7 +1108,7 @@ ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
   if (!SubIdx)
     return MIB.addReg(Reg, State);
 
-  if (Register::isPhysicalRegister(Reg))
+  if (Register(Reg).isPhysical())
     return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
   return MIB.addReg(Reg, State, SubIdx);
 }
diff --git a/llvm/lib/Target/ARM/ARMLatencyMutations.cpp b/llvm/lib/Target/ARM/ARMLatencyMutations.cpp
@@ -802,7 +802,7 @@ signed M85Overrides::modifyMixedWidthFP(const MachineInstr *SrcMI,
             OP.getSubReg() == ARM::ssub_1)
           return 1;
     }
-  } else if (Register::isPhysicalRegister(RegID)) {
+  } else if (Register(RegID).isPhysical()) {
     // Note that when the producer is narrower, not all of the producers
     // may be present in the scheduling graph; somewhere earlier in the
     // compiler, an implicit def/use of the aliased full register gets
diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -223,8 +223,8 @@ static bool areCombinableOperations(const TargetRegisterInfo *TRI,
   return true;
 }
 
-static bool isEvenReg(unsigned Reg) {
-  assert(Register::isPhysicalRegister(Reg));
+static bool isEvenReg(Register Reg) {
+  assert(Reg.isPhysical());
   if (Hexagon::IntRegsRegClass.contains(Reg))
     return (Reg - Hexagon::R0) % 2 == 0;
   if (Hexagon::HvxVRRegClass.contains(Reg))
@@ -546,7 +546,7 @@ MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr &I1,
     // is even.
     bool IsI1LowReg = (I2DestReg - I1DestReg) == 1;
     bool IsI2LowReg = (I1DestReg - I2DestReg) == 1;
-    unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg;
+    Register FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg;
     if ((!IsI1LowReg && !IsI2LowReg) || !isEvenReg(FirstRegIndex))
       continue;
 
diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
@@ -275,7 +275,7 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
       return false;
   }
 
-  unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
+  Register cmpReg1, cmpOp2;
   cmpReg1 = MI.getOperand(1).getReg();
 
   if (secondReg) {
@@ -290,7 +290,7 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
     // at machine code level, we don't need this, but if we decide
     // to move new value jump prior to RA, we would be needing this.
     MachineRegisterInfo &MRI = MF.getRegInfo();
-    if (!Register::isPhysicalRegister(cmpOp2)) {
+    if (!cmpOp2.isPhysical()) {
       MachineInstr *def = MRI.getVRegDef(cmpOp2);
       if (def->getOpcode() == TargetOpcode::COPY)
         return false;
@@ -480,7 +480,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
     bool foundJump    = false;
     bool foundCompare = false;
     bool invertPredicate = false;
-    unsigned predReg = 0; // predicate reg of the jump.
+    Register predReg; // predicate reg of the jump.
     unsigned cmpReg1 = 0;
     int cmpOp2 = 0;
     MachineBasicBlock::iterator jmpPos;
@@ -516,7 +516,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
         jmpPos = MII;
         jmpInstr = &MI;
         predReg = MI.getOperand(0).getReg();
-        afterRA = Register::isPhysicalRegister(predReg);
+        afterRA = predReg.isPhysical();
 
         // If ifconverter had not messed up with the kill flags of the
         // operands, the following check on the kill flag would suffice.
diff --git a/llvm/lib/Target/Hexagon/RDFCopy.cpp b/llvm/lib/Target/Hexagon/RDFCopy.cpp
@@ -44,8 +44,8 @@ bool CopyPropagation::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) {
       const MachineOperand &Src = MI->getOperand(1);
       RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg());
       RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg());
-      assert(Register::isPhysicalRegister(DstR.Reg));
-      assert(Register::isPhysicalRegister(SrcR.Reg));
+      assert(Register(DstR.Reg).isPhysical());
+      assert(Register(SrcR.Reg).isPhysical());
       const TargetRegisterInfo &TRI = DFG.getTRI();
       if (TRI.getMinimalPhysRegClass(DstR.Reg) !=
           TRI.getMinimalPhysRegClass(SrcR.Reg))
diff --git a/llvm/lib/Target/M68k/M68kRegisterInfo.cpp b/llvm/lib/Target/M68k/M68kRegisterInfo.cpp
@@ -83,8 +83,7 @@ M68kRegisterInfo::getMatchingMegaReg(unsigned Reg,
 
 const TargetRegisterClass *
 M68kRegisterInfo::getMaximalPhysRegClass(unsigned reg, MVT VT) const {
-  assert(Register::isPhysicalRegister(reg) &&
-         "reg must be a physical register");
+  assert(Register(reg).isPhysical() && "reg must be a physical register");
 
   // Pick the most sub register class of the right type that contains
   // this physreg.

Original file line number	Diff line number	Diff line change
`@@ -111,7 +111,7 @@ struct RegisterRef {`
`111`	`111`	`}`
`112`	`112`
`113`	`113`	`static constexpr bool isRegId(unsigned Id) {`
`114`		`- return Register::isPhysicalRegister(Id);`
	`114`	`+ return Register(Id).isPhysical();`
`115`	`115`	`}`
`116`	`116`	`static constexpr bool isUnitId(unsigned Id) {`
`117`	`117`	`return Register(Id).isVirtual();`
Original file line number	Diff line number	Diff line change
`@@ -525,7 +525,7 @@ void llvm::calculateDbgEntityHistory(const MachineFunction *MF,`
`525`	`525`	`// Don't consider SP to be clobbered by register masks.`
`526`	`526`	`for (auto It : RegVars) {`
`527`	`527`	`unsigned int Reg = It.first;`
`528`		`- if (Reg != SP && Register::isPhysicalRegister(Reg) &&`
	`528`	`+ if (Reg != SP && Register(Reg).isPhysical() &&`
`529`	`529`	`MO.clobbersPhysReg(Reg))`
`530`	`530`	`RegsToClobber.push_back(Reg);`
`531`	`531`	`}`
Original file line number	Diff line number	Diff line change
`@@ -564,7 +564,7 @@ DIE &DwarfCompileUnit::updateSubprogramScopeDIE(const DISubprogram *SP,`
`564`	`564`	`TFI->getDwarfFrameBase(*Asm->MF);`
`565`	`565`	`switch (FrameBase.Kind) {`
`566`	`566`	`case TargetFrameLowering::DwarfFrameBase::Register: {`
`567`		`- if (Register::isPhysicalRegister(FrameBase.Location.Reg)) {`
	`567`	`+ if (Register(FrameBase.Location.Reg).isPhysical()) {`
`568`	`568`	`MachineLocation Location(FrameBase.Location.Reg);`
`569`	`569`	`addAddress(*SPDie, dwarf::DW_AT_frame_base, Location);`
`570`	`570`	`}`
Original file line number	Diff line number	Diff line change
`@@ -216,7 +216,7 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,`
`216`	`216`	`report_fatal_error("Use not jointly dominated by defs.");`
`217`	`217`	`}`
`218`	`218`
`219`		`- if (Register::isPhysicalRegister(PhysReg)) {`
	`219`	`+ if (Register(PhysReg).isPhysical()) {`
`220`	`220`	`const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();`
`221`	`221`	`bool IsLiveIn = MBB->isLiveIn(PhysReg);`
`222`	`222`	`for (MCRegAliasIterator Alias(PhysReg, TRI, false); !IsLiveIn && Alias.isValid(); ++Alias)`