uefi: Add PciRootBridgeIo::configuration() to query acpi table info

Author: seijikun

uefi/CHANGELOG.md

@@ -2,6 +2,7 @@
 
 ## Added
 - Added `proto::ata::AtaRequestBuilder::read_pio()`.
+- Added `proto::pci::root_bridge::PciRootBridgeIo::configuration()`.
 
 ## Changed
 - Changed ordering of `proto::pci::PciIoAddress` to (bus -> dev -> fun -> reg -> ext_reg).

uefi/src/proto/pci/configuration.rs

@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0
+
+//! Pci root bus resource configuration descriptor parsing.
+
+use core::ffi::c_void;
+use core::ptr;
+
+use alloc::{slice, vec::Vec};
+
+/// Represents the type of resource described by a QWORD Address Space Descriptor.
+/// This corresponds to the `resource_type` field at offset 0x03 in the descriptor.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(u8)]
+pub enum ResourceRangeType {
+    /// Memory Range (value = 0)
+    /// Indicates that the descriptor describes a memory-mapped address range.
+    /// Commonly used for MMIO regions decoded by the PCI root bridge.
+    Memory = 0,
+
+    /// I/O Range (value = 1)
+    /// Indicates that the descriptor describes a legacy I/O port range.
+    /// Used for devices that communicate via port-mapped I/O.
+    Io = 1,
+
+    /// Bus Number Range (value = 2)
+    /// Indicates that the descriptor describes a range of PCI bus numbers.
+    /// Used to define the bus hierarchy behind a PCI root bridge.
+    Bus = 2,
+
+    /// Unknown or vendor-specific resource type.
+    /// Captures any unrecognized value for forward compatibility.
+    Unknown(u8),
+}
+impl From<u8> for ResourceRangeType {
+    fn from(value: u8) -> Self {
+        match value {
+            0 => Self::Memory,
+            1 => Self::Io,
+            2 => Self::Bus,
+            other => Self::Unknown(other),
+        }
+    }
+}
+
+/// Represents a parsed QWORD Address Space Descriptor from UEFI.
+/// This structure describes a decoded resource range for a PCI root bridge.
+#[derive(Clone, Debug)]
+pub struct QwordAddressSpaceDescriptor {
+    /// Type of resource: Memory, I/O, Bus, or Unknown.
+    pub resource_range_type: ResourceRangeType,
+
+    /// General flags that describe decode behavior (e.g., positive decode).
+    pub general_flags: u8,
+
+    /// Type-specific flags (e.g., cacheability for memory).
+    pub type_specific_flags: u8,
+
+    /// Granularity of the address space (typically 32 or 64).
+    /// Indicates whether the range is 32-bit or 64-bit.
+    pub granularity: u64,
+
+    /// Minimum address of the range (inclusive).
+    pub address_min: u64,
+
+    /// Maximum address of the range (inclusive).
+    pub address_max: u64,
+
+    /// Translation offset to convert host address to PCI address.
+    /// Usually zero unless the bridge remaps addresses.
+    pub translation_offset: u64,
+
+    /// Length of the address range (in bytes or bus numbers).
+    pub address_length: u64,
+}
+
+const PCI_RESTBL_QWORDADDRSPEC_TAG: u8 = 0x8a;
+const PCI_RESTBL_END_TAG: u8 = 0x79;
+
+/// Parses a list of QWORD Address Space Descriptors from a raw memory region.
+/// Stops when it encounters an End Tag descriptor (type 0x79).
+pub(crate) fn parse(base: *const c_void) -> Vec<QwordAddressSpaceDescriptor> {
+    let base: *const u8 = base.cast();
+
+    // Phase 1: determine total length
+    let mut offset = 0;
+    loop {
+        let tag = unsafe { ptr::read(base.add(offset)) };
+        offset += match tag {
+            PCI_RESTBL_QWORDADDRSPEC_TAG => 3 + 0x2B,
+            PCI_RESTBL_END_TAG => break,
+            _ => return Vec::new(), // Unknown tag - bailing
+        };
+    }
+
+    // Phase 2: parse descriptors from resource table
+    let mut bfr: &[u8] = unsafe { slice::from_raw_parts(base, offset) };
+    let mut descriptors = Vec::new();
+    while !bfr.is_empty() {
+        match bfr[0] {
+            PCI_RESTBL_QWORDADDRSPEC_TAG => {
+                let descriptor = QwordAddressSpaceDescriptor {
+                    resource_range_type: ResourceRangeType::from(bfr[0x03]),
+                    general_flags: bfr[0x04],
+                    type_specific_flags: bfr[0x05],
+                    granularity: u64::from_le_bytes(bfr[0x06..0x06 + 8].try_into().unwrap()),
+                    address_min: u64::from_le_bytes(bfr[0x0E..0x0E + 8].try_into().unwrap()),
+                    address_max: u64::from_le_bytes(bfr[0x16..0x16 + 8].try_into().unwrap()),
+                    translation_offset: u64::from_le_bytes(bfr[0x1E..0x1E + 8].try_into().unwrap()),
+                    address_length: u64::from_le_bytes(bfr[0x26..0x26 + 8].try_into().unwrap()),
+                };
+                descriptors.push(descriptor);
+
+                bfr = &bfr[3 + 0x2B..];
+            }
+            _ => break,
+        }
+    }
+
+    descriptors
+}

uefi/src/proto/pci/mod.rs

@@ -6,6 +6,7 @@ use core::cmp::Ordering;
 
 use uefi_raw::protocol::pci::root_bridge::PciRootBridgeIoProtocolWidth;
 
+pub mod configuration;
 pub mod root_bridge;
 
 /// IO Address for PCI/register IO operations
@@ -121,6 +122,34 @@ impl Ord for PciIoAddress {
     }
 }
 
+// --------------------------------------------------------------------------------------------
+
+/// Fully qualified pci address. This address is valid across root bridges.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash, PartialOrd, Ord)]
+pub struct FullPciIoAddress {
+    /// PCI segment number
+    segment: u32,
+    /// Subsequent PCI address
+    addr: PciIoAddress,
+}
+impl FullPciIoAddress {
+    pub(crate) fn new(segment: u32, addr: PciIoAddress) -> Self {
+        Self { segment, addr }
+    }
+
+    /// Get the segment number this address belongs to.
+    pub fn segment(&self) -> u32 {
+        self.segment
+    }
+
+    /// Get the internal RootBridge-specific portion of the address.
+    pub fn addr(&self) -> PciIoAddress {
+        self.addr
+    }
+}
+
+// ############################################################################################
+
 /// Trait implemented by all data types that can natively be read from a PCI device.
 /// Note: Not all of them have to actually be supported by the hardware at hand.
 pub trait PciIoUnit: Sized + Default {}

uefi/src/proto/pci/root_bridge.rs

@@ -2,10 +2,14 @@
 
 //! PCI Root Bridge protocol.
 
-use core::ptr;
+use core::{ffi::c_void, ptr};
 
 use super::{PciIoAddress, PciIoUnit, encode_io_mode_and_unit};
-use crate::StatusExt;
+use crate::{
+    StatusExt,
+    proto::pci::configuration::{self, QwordAddressSpaceDescriptor},
+};
+use alloc::vec::Vec;
 use uefi_macros::unsafe_protocol;
 use uefi_raw::protocol::pci::root_bridge::{PciRootBridgeIoAccess, PciRootBridgeIoProtocol};
 
@@ -52,7 +56,21 @@ impl PciRootBridgeIo {
     // TODO: map & unmap & copy memory
     // TODO: buffer management
     // TODO: get/set attributes
-    // TODO: configuration / resource settings
+
+    /// Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI resource descriptors.
+    ///
+    /// The returned list of descriptors contains information about bus, memory and io ranges that were set up
+    /// by the firmware.
+    ///
+    /// # Errors
+    /// - [`Status::UNSUPPORTED`] The current configuration of this PCI root bridge could not be retrieved.
+    pub fn configuration(&self) -> crate::Result<Vec<QwordAddressSpaceDescriptor>> {
+        let mut resources: *const c_void = ptr::null();
+        unsafe {
+            ((self.0.configuration)(&self.0, &mut resources))
+                .to_result_with_val(|| configuration::parse(resources))
+        }
+    }
 }
 
 /// Struct for performing PCI I/O operations on a root bridge.