Merge pull request #112 from siliconcompiler/rc2

update names of classes to match SC

Author: gadfort

examples/chip/chip.py

@@ -1,11 +1,11 @@
 import subprocess
 
-from siliconcompiler import DesignSchema
+from siliconcompiler import Design
 
 from lambdalib.padring import Padring
 
 
-class Chip(DesignSchema):
+class Chip(Design):
     def __init__(self):
 
         name = 'chip'

lambdalib/__init__.py

@@ -1,4 +1,4 @@
-from siliconcompiler import DesignSchema, ASICProject
+from siliconcompiler import Design, ASICProject
 
 #  individual modules
 from lambdalib import auxlib
@@ -9,11 +9,11 @@
 from lambdalib import ramlib
 from lambdalib import veclib
 
-__version__ = "0.4.0-rc1"
+__version__ = "0.4.0-rc2"
 
 
-class LambalibTechLibrary(DesignSchema):
-    """A DesignSchema class to manage a lambda library and its associated technology libraries.
+class LambalibTechLibrary(Design):
+    """A Design class to manage a lambda library and its associated technology libraries.
 
     This class encapsulates a main lambda library cell and a list of technology
     libraries, providing a mechanism to alias them within an ASIC project.

lambdalib/auxlib/__init__.py

@@ -1,4 +1,4 @@
-from siliconcompiler import DesignSchema
+from siliconcompiler import Design
 
 from .la_drsync.la_drsync import Drsync
 from .la_dsync.la_dsync import Dsync
@@ -47,7 +47,7 @@
            'Tbuf']
 
 
-class AUXLib(DesignSchema):
+class AUXLib(Design):
     def __init__(self):
         super().__init__("la_auxlib")
 

lambdalib/fpgalib/__init__.py

@@ -1,4 +1,4 @@
-from siliconcompiler import DesignSchema
+from siliconcompiler import Design
 
 from .la_lut4.la_lut4 import Lut4
 from .la_ble4p0.la_ble4p0 import Ble4p0
@@ -9,7 +9,7 @@
            'Lut4']
 
 
-class FPGALib(DesignSchema):
+class FPGALib(Design):
     def __init__(self):
         super().__init__("la_fpgalib")
 

lambdalib/iolib/__init__.py

@@ -1,4 +1,4 @@
-from siliconcompiler import DesignSchema
+from siliconcompiler import Design
 
 from .la_ioanalog.la_ioanalog import Ioanalog
 from .la_iobidir.la_iobidir import Iobidir
@@ -35,7 +35,7 @@
            'Ioxtal']
 
 
-class IOLib(DesignSchema):
+class IOLib(Design):
     def __init__(self):
         super().__init__("la_iolib")
 

lambdalib/lambdalib.py

@@ -1,9 +1,9 @@
 from pathlib import Path
 from typing import Union, List
-from siliconcompiler import DesignSchema
+from siliconcompiler import Design
 
 
-class Lambda(DesignSchema):
+class Lambda(Design):
     def __init__(self,
                  name: str,
                  path: Union[str, Path],

lambdalib/ramlib/__init__.py

@@ -1,4 +1,4 @@
-from siliconcompiler import DesignSchema
+from siliconcompiler import Design
 
 from .la_asyncfifo.la_asyncfifo import Asyncfifo
 from .la_syncfifo.la_syncfifo import Syncfifo
@@ -11,7 +11,7 @@
            'Spram']
 
 
-class RAMLib(DesignSchema):
+class RAMLib(Design):
     def __init__(self):
         super().__init__("la_ramlib")
 

lambdalib/stdlib/__init__.py

@@ -1,4 +1,4 @@
-from siliconcompiler import DesignSchema
+from siliconcompiler import Design
 
 from .la_and2.la_and2 import And2
 from .la_and3.la_and3 import And3
@@ -195,7 +195,7 @@
            'Xor4']
 
 
-class STDLib(DesignSchema):
+class STDLib(Design):
     def __init__(self):
         super().__init__("la_stdlib")
 

lambdalib/veclib/__init__.py

@@ -1,4 +1,4 @@
-from siliconcompiler import DesignSchema
+from siliconcompiler import Design
 
 from .la_vbuf.la_vbuf import Vbuf
 from .la_vinv.la_vinv import Vinv
@@ -25,7 +25,7 @@
            'Vmux8']
 
 
-class STDLib(DesignSchema):
+class STDLib(Design):
     def __init__(self):
         super().__init__("la_veclib")