@@ -124,17 +124,17 @@ Nucleo_144.menu.pnum.NUCLEO_L496ZG.build.variant=Nucleo_144/NUCLEO_L496ZG
124124Nucleo_144.menu.pnum.NUCLEO_L496ZG.build.cmsis_lib_gcc=arm_cortexM4lf_math
125125
126126# NUCLEO_L496ZG-P board
127- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P =Nucleo L496ZG-P
128- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .node=NODE_L496ZG
129- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .upload.maximum_size=1048576
130- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .upload.maximum_data_size=327680
131- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .build.mcu=cortex-m4
132- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
133- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .build.board=NUCLEO_L496ZG_P
134- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .build.series=STM32L4xx
135- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .build.product_line=STM32L496xx
136- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .build.variant=Nucleo_144/NUCLEO_L496ZG
137- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .build.cmsis_lib_gcc=arm_cortexM4lf_math
127+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P =Nucleo L496ZG-P
128+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .node=NODE_L496ZG
129+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .upload.maximum_size=1048576
130+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .upload.maximum_data_size=327680
131+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .build.mcu=cortex-m4
132+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
133+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .build.board=NUCLEO_L496ZG_P
134+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .build.series=STM32L4xx
135+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .build.product_line=STM32L496xx
136+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .build.variant=Nucleo_144/NUCLEO_L496ZG
137+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .build.cmsis_lib_gcc=arm_cortexM4lf_math
138138
139139# NUCLEO_L4R5ZI board
140140Nucleo_144.menu.pnum.NUCLEO_L4R5ZI=Nucleo L4R5ZI
@@ -150,17 +150,17 @@ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.build.variant=Nucleo_144/NUCLEO_L4R5ZI
150150Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.build.cmsis_lib_gcc=arm_cortexM4lf_math
151151
152152# NUCLEO_L4R5ZI-P board
153- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P =Nucleo L4R5ZI-P
154- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .node=NODE_L4R5ZI
155- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .upload.maximum_size=2097152
156- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .upload.maximum_data_size=655360
157- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .build.mcu=cortex-m4
158- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
159- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .build.board=NUCLEO_L4R5ZI_P
160- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .build.series=STM32L4xx
161- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .build.product_line=STM32L4R5xx
162- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .build.variant=Nucleo_144/NUCLEO_L4R5ZI
163- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .build.cmsis_lib_gcc=arm_cortexM4lf_math
153+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P =Nucleo L4R5ZI-P
154+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .node=NODE_L4R5ZI
155+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .upload.maximum_size=2097152
156+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .upload.maximum_data_size=655360
157+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .build.mcu=cortex-m4
158+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
159+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .build.board=NUCLEO_L4R5ZI_P
160+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .build.series=STM32L4xx
161+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .build.product_line=STM32L4R5xx
162+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .build.variant=Nucleo_144/NUCLEO_L4R5ZI
163+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .build.cmsis_lib_gcc=arm_cortexM4lf_math
164164
165165# Upload menu
166166Nucleo_144.menu.upload_method.MassStorage=Mass Storage
@@ -408,17 +408,17 @@ Nucleo_64.menu.pnum.NUCLEO_L452RE.build.variant=Nucleo_64/NUCLEO_L452RE
408408Nucleo_64.menu.pnum.NUCLEO_L452RE.build.cmsis_lib_gcc=arm_cortexM4lf_math
409409
410410# NUCLEO_L452RE-P board
411- Nucleo_64.menu.pnum.NUCLEO_L452REP =Nucleo L452RE-P
412- Nucleo_64.menu.pnum.NUCLEO_L452REP .node=NODE_L452RE
413- Nucleo_64.menu.pnum.NUCLEO_L452REP .upload.maximum_size=524288
414- Nucleo_64.menu.pnum.NUCLEO_L452REP .upload.maximum_data_size=163840
415- Nucleo_64.menu.pnum.NUCLEO_L452REP .build.mcu=cortex-m4
416- Nucleo_64.menu.pnum.NUCLEO_L452REP .build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
417- Nucleo_64.menu.pnum.NUCLEO_L452REP .build.board=NUCLEO_L452RE_P
418- Nucleo_64.menu.pnum.NUCLEO_L452REP .build.series=STM32L4xx
419- Nucleo_64.menu.pnum.NUCLEO_L452REP .build.product_line=STM32L452xx
420- Nucleo_64.menu.pnum.NUCLEO_L452REP .build.variant=Nucleo_64/NUCLEO_L452RE
421- Nucleo_64.menu.pnum.NUCLEO_L452REP .build.cmsis_lib_gcc=arm_cortexM4lf_math
411+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P =Nucleo L452RE-P
412+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .node=NODE_L452RE
413+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .upload.maximum_size=524288
414+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .upload.maximum_data_size=163840
415+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .build.mcu=cortex-m4
416+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
417+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .build.board=NUCLEO_L452RE_P
418+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .build.series=STM32L4xx
419+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .build.product_line=STM32L452xx
420+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .build.variant=Nucleo_64/NUCLEO_L452RE
421+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .build.cmsis_lib_gcc=arm_cortexM4lf_math
422422
423423# NUCLEO_L476RG board
424424# Support: Serial1 (USART1 on PA10, PA9)
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