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f74064054@mail.ncku.edu.tw
committed
Finish the test for rv32i comformance tests
I have modified the emu-rv32i for supporting riscv-compliance test-suite. However, it is needed to copy the makefile.include to the specified directory which is explained in README.md.
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‎.gitignore‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ test1
33
sig.txt
44
rom.v
55
debug.txt
6-
CSR.h
76
# ignore generated files
87
work
98
*.mem
9+
*.signature.output

‎README.md‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,15 +24,19 @@ Passed RV32IC compliance tests from https://github.com/riscv/riscv-compliance
2424
Assume `emu-rv32i` in `$PATH` environment variable.
2525
```shell
2626
$ git clone https://github.com/riscv/riscv-compliance
27-
$ cd riscv-compliance
27+
$ cd rv32emu
28+
$ cp rv32emu ../riscv-compliance/riscv-target
29+
$ cd ../riscv-compliance
2830
$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32i TARGET_SIM=emu-rv32i variant
2931
```
3032
- Run RV32IMC compliance tests.
3133
Assume `emu-rv32i` in `$PATH` environment variable.
3234
```shell
3335
$ git clone https://github.com/riscv/riscv-compliance
36+
$ cd rv32emu
37+
$ cp rv32emu ../riscv-compliance/riscv-target # If having copied the makefile.include to riscv-compliance, it can be ignored.
3438
$ cd riscv-compliance
35-
$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32imc TARGET_SIM=emu-rv32i variant
39+
$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32imc TARGET_SIM=/abs/path/to/emu-rv32i variant
3640
```
3741

3842
Compiling and running simple code:

‎emu-rv32i.c‎

Lines changed: 45 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,8 @@
2121
#include <unistd.h>
2222

2323
/* uncomment this for an instruction trace and other debug outputs */
24-
// #define DEBUG_OUTPUT
25-
// #define DEBUG_EXTRA
24+
#define DEBUG_OUTPUT
25+
#define DEBUG_EXTRA
2626

2727
#define STRICT_RV32I
2828
#define FALSE (0)
@@ -655,20 +655,20 @@ void raise_exception(uint32_t cause, uint32_t tval)
655655
return;
656656
}
657657

658-
switch (cause) {
659-
case CAUSE_MACHINE_ECALL:
660-
printf("Unimplement Machine ecall!\n");
661-
return;
662-
case CAUSE_USER_ECALL:
663-
printf("Unimplement User ecall!\n");
664-
return;
665-
case CAUSE_SUPERVISOR_ECALL:
666-
printf("Unimplement Supervisor ecall!\n");
667-
return;
668-
case CAUSE_HYPERVISOR_ECALL:
669-
printf("Unimplement Hypervisor ecall!\n");
670-
return;
671-
}
658+
// switch (cause) {
659+
// case CAUSE_MACHINE_ECALL:
660+
// printf("Unimplement Machine ecall!\n");
661+
// return;
662+
// case CAUSE_USER_ECALL:
663+
// printf("Unimplement User ecall!\n");
664+
// return;
665+
// case CAUSE_SUPERVISOR_ECALL:
666+
// printf("Unimplement Supervisor ecall!\n");
667+
// return;
668+
// case CAUSE_HYPERVISOR_ECALL:
669+
// printf("Unimplement Hypervisor ecall!\n");
670+
// return;
671+
// }
672672

673673
if (priv <= PRV_S) {
674674
/* delegate the exception to the supervisor priviledge */
@@ -2785,9 +2785,15 @@ void riscv_cpu_interp_x32()
27852785

27862786
/* test for misaligned fetches , in order to match the compressed
27872787
* instruction. */
2788+
#ifdef RV32C
27882789
if (next_pc & 0x1) {
27892790
raise_exception(CAUSE_MISALIGNED_FETCH, next_pc);
27902791
}
2792+
#else
2793+
if (next_pc & 0x3) {
2794+
raise_exception(CAUSE_MISALIGNED_FETCH, next_pc);
2795+
}
2796+
#endif
27912797

27922798
/* update current PC */
27932799
pc = next_pc;
@@ -2808,23 +2814,33 @@ int main(int argc, char **argv)
28082814
setvbuf(stdout, NULL, _IONBF, 0);
28092815
/* parse command line */
28102816
const char *elf_file = NULL;
2811-
const char *signature_file = NULL;
2817+
int output_flag = 0;
28122818
const char *output_file = NULL;
2819+
const char *elf_name = NULL;
2820+
const char* signature_file = NULL;
28132821
int cmd_opt = 0;
28142822
struct option opts[] = {{"elf", 1, NULL, 'e'},
2815-
{"signature", 1, NULL, 's'},
2816-
{"output", 1, NULL, 'o'}};
2823+
{"verify", 1, NULL, 'v'},
2824+
{"signaturedump", 0, NULL, 's'}};
28172825
const char *optstring = "e:s:o:";
28182826
while ((cmd_opt = getopt_long(argc, argv, optstring, opts, NULL)) != -1) {
28192827
switch (cmd_opt) {
28202828
case 'e':
28212829
elf_file = optarg;
2830+
elf_name = strtok(strdup(elf_file), ".");
2831+
printf("%s\n", elf_name);
2832+
output_file = malloc(strlen(elf_name) + 30);
2833+
memset(output_file, '\0', strlen(elf_name) + 30);
2834+
strcat(output_file, elf_name);
2835+
strcat(output_file, ".signature.output");
2836+
printf("signature.output : %s\n", output_file);
28222837
break;
2823-
case 's':
2824-
signature_file = optarg;
2838+
case 'v':
2839+
//signature_file = optarg;
28252840
break;
2826-
case 'o':
2827-
output_file = optarg;
2841+
case 's':
2842+
//output_file = optarg;
2843+
output_flag = 1;
28282844
break;
28292845
default:
28302846
printf("Unknow argument: %s\n", optarg);
@@ -2900,11 +2916,15 @@ int main(int argc, char **argv)
29002916
while ((scn = elf_nextscn(elf, scn)) != NULL) {
29012917
gelf_getshdr(scn, &shdr);
29022918
const char *name = elf_strptr(elf, shstrndx, shdr.sh_name);
2903-
2919+
printf("section name: %s\n", name);
2920+
printf("Type: %d\n", shdr.sh_type);
29042921
if (shdr.sh_type == SHT_PROGBITS) {
29052922
if (strcmp(name, ".text") == 0) {
29062923
ram_start = shdr.sh_addr;
29072924
break;
2925+
}else if(strcmp(name, ".text.init") == 0){
2926+
ram_start = shdr.sh_addr;
2927+
break;
29082928
}
29092929
}
29102930
}
@@ -3051,6 +3071,7 @@ int main(int argc, char **argv)
30513071
fclose(sf);
30523072
}
30533073
if (output_file) {
3074+
30543075
FILE *of = fopen(output_file, "w");
30553076
int size = end_signature - begin_signature;
30563077
for (int i = 0; i < size / 4; i++) {

‎rv32emu/compliance_io.h‎

Lines changed: 240 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,240 @@
1+
// RISC-V Compliance IO Test Header File
2+
3+
/*
4+
* Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
5+
*
6+
* Licensed under the Apache License, Version 2.0 (the "License");
7+
* you may not use this file except in compliance with the License.
8+
* You may obtain a copy of the License at
9+
*
10+
* http://www.apache.org/licenses/LICENSE-2.0
11+
*
12+
* Unless required by applicable law or agreed to in writing, software
13+
* distributed under the License is distributed on an "AS IS" BASIS,
14+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
15+
* either express or implied.
16+
*
17+
* See the License for the specific language governing permissions and
18+
* limitations under the License.
19+
*
20+
*/
21+
22+
23+
//
24+
// In general the following registers are reserved
25+
// ra, a0, t0, t1
26+
// x1, x10 x5, x6
27+
// new reserve x31
28+
//
29+
30+
#ifndef _COMPLIANCE_IO_H
31+
#define _COMPLIANCE_IO_H
32+
33+
#define RVTEST_IO_QUIET
34+
35+
//-----------------------------------------------------------------------
36+
// RV IO Macros (Character transfer by custom instruction)
37+
//-----------------------------------------------------------------------
38+
#define STRINGIFY(x) #x
39+
#define TOSTRING(x) STRINGIFY(x)
40+
41+
#define RVTEST_CUSTOM1 0x0005200B
42+
43+
#ifdef RVTEST_IO_QUIET
44+
45+
#define RVTEST_IO_INIT
46+
#define RVTEST_IO_WRITE_STR(_SP, _STR)
47+
#define RVTEST_IO_CHECK()
48+
#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
49+
#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I)
50+
#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I)
51+
52+
#else
53+
54+
#define RSIZE 4
55+
// _SP = (volatile register)
56+
#define LOCAL_IO_PUSH(_SP) \
57+
la _SP, begin_regstate; \
58+
sw x1, (1*RSIZE)(_SP); \
59+
sw x5, (5*RSIZE)(_SP); \
60+
sw x6, (6*RSIZE)(_SP); \
61+
sw x8, (8*RSIZE)(_SP); \
62+
sw x10, (10*RSIZE)(_SP);
63+
64+
// _SP = (volatile register)
65+
#define LOCAL_IO_POP(_SP) \
66+
la _SP, begin_regstate; \
67+
lw x1, (1*RSIZE)(_SP); \
68+
lw x5, (5*RSIZE)(_SP); \
69+
lw x6, (6*RSIZE)(_SP); \
70+
lw x8, (8*RSIZE)(_SP); \
71+
lw x10, (10*RSIZE)(_SP);
72+
73+
#define LOCAL_IO_WRITE_GPR(_R) \
74+
mv a0, _R; \
75+
jal FN_WriteA0;
76+
77+
#define LOCAL_IO_WRITE_FPR(_F) \
78+
fmv.x.s a0, _F; \
79+
jal FN_WriteA0;
80+
81+
#define LOCAL_IO_WRITE_DFPR(_V1, _V2) \
82+
mv a0, _V1; \
83+
jal FN_WriteA0; \
84+
mv a0, _V2; \
85+
jal FN_WriteA0; \
86+
87+
#define LOCAL_IO_PUTC(_R) \
88+
.word RVTEST_CUSTOM1; \
89+
90+
#define RVTEST_IO_INIT
91+
92+
// Assertion violation: file file.c, line 1234: (expr)
93+
// _SP = (volatile register)
94+
// _R = GPR
95+
// _I = Immediate
96+
#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I) \
97+
LOCAL_IO_PUSH(_SP) \
98+
mv s0, _R; \
99+
li t0, _I; \
100+
beq s0, t0, 20002f; \
101+
LOCAL_IO_WRITE_STR("Assertion violation: file "); \
102+
LOCAL_IO_WRITE_STR(__FILE__); \
103+
LOCAL_IO_WRITE_STR(", line "); \
104+
LOCAL_IO_WRITE_STR(TOSTRING(__LINE__)); \
105+
LOCAL_IO_WRITE_STR(": "); \
106+
LOCAL_IO_WRITE_STR(# _R); \
107+
LOCAL_IO_WRITE_STR("("); \
108+
LOCAL_IO_WRITE_GPR(s0); \
109+
LOCAL_IO_WRITE_STR(") != "); \
110+
LOCAL_IO_WRITE_STR(# _I); \
111+
LOCAL_IO_WRITE_STR("\n"); \
112+
li TESTNUM, 100; \
113+
RVTEST_FAIL; \
114+
20002: \
115+
LOCAL_IO_POP(_SP)
116+
117+
// _F = FPR
118+
// _C = GPR
119+
// _I = Immediate
120+
#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _C, _I) \
121+
fmv.x.s t0, _F; \
122+
beq _C, t0, 20003f; \
123+
LOCAL_IO_WRITE_STR("Assertion violation: file "); \
124+
LOCAL_IO_WRITE_STR(__FILE__); \
125+
LOCAL_IO_WRITE_STR(", line "); \
126+
LOCAL_IO_WRITE_STR(TOSTRING(__LINE__)); \
127+
LOCAL_IO_WRITE_STR(": "); \
128+
LOCAL_IO_WRITE_STR(# _F); \
129+
LOCAL_IO_WRITE_STR("("); \
130+
LOCAL_IO_WRITE_FPR(_F); \
131+
LOCAL_IO_WRITE_STR(") != "); \
132+
LOCAL_IO_WRITE_STR(# _I); \
133+
LOCAL_IO_WRITE_STR("\n"); \
134+
li TESTNUM, 100; \
135+
RVTEST_FAIL; \
136+
20003:
137+
138+
// _D = DFPR
139+
// _R = GPR
140+
// _I = Immediate
141+
#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) \
142+
fmv.x.d t0, _D; \
143+
beq _R, t0, 20005f; \
144+
LOCAL_IO_WRITE_STR("Assertion violation: file "); \
145+
LOCAL_IO_WRITE_STR(__FILE__); \
146+
LOCAL_IO_WRITE_STR(", line "); \
147+
LOCAL_IO_WRITE_STR(TOSTRING(__LINE__)); \
148+
LOCAL_IO_WRITE_STR(": "); \
149+
LOCAL_IO_WRITE_STR(# _D); \
150+
LOCAL_IO_WRITE_STR("("); \
151+
LOCAL_IO_WRITE_DFPR(_D); \
152+
LOCAL_IO_WRITE_STR(") != "); \
153+
LOCAL_IO_WRITE_STR(# _I); \
154+
LOCAL_IO_WRITE_STR("\n"); \
155+
li TESTNUM, 100; \
156+
RVTEST_FAIL; \
157+
20005:
158+
159+
// _SP = (volatile register)
160+
#define LOCAL_IO_WRITE_STR(_STR) RVTEST_IO_WRITE_STR(x31, _STR)
161+
#define RVTEST_IO_WRITE_STR(_SP, _STR) \
162+
LOCAL_IO_PUSH(_SP) \
163+
.section .data.string; \
164+
20001: \
165+
.string _STR; \
166+
.section .text.init; \
167+
la a0, 20001b; \
168+
jal FN_WriteStr; \
169+
LOCAL_IO_POP(_SP)
170+
171+
// generate assertion listing
172+
#define LOCAL_CHECK() RVTEST_IO_CHECK()
173+
#define RVTEST_IO_CHECK() \
174+
li zero, -1; \
175+
176+
//
177+
// FN_WriteStr: Uses a0, t0
178+
//
179+
FN_WriteStr:
180+
mv t0, a0;
181+
10000:
182+
lbu a0, (t0);
183+
addi t0, t0, 1;
184+
beq a0, zero, 10000f;
185+
LOCAL_IO_PUTC(a0);
186+
j 10000b;
187+
10000:
188+
ret;
189+
190+
//
191+
// FN_WriteA0: write register a0(x10) (destroys a0(x10), t0-t2(x5-x7))
192+
//
193+
FN_WriteA0:
194+
mv t0, a0
195+
// determine architectural register width
196+
li a0, -1
197+
srli a0, a0, 31
198+
srli a0, a0, 1
199+
bnez a0, FN_WriteA0_64
200+
201+
FN_WriteA0_32:
202+
// reverse register when xlen is 32
203+
li t1, 8
204+
10000: slli t2, t2, 4
205+
andi a0, t0, 0xf
206+
srli t0, t0, 4
207+
or t2, t2, a0
208+
addi t1, t1, -1
209+
bnez t1, 10000b
210+
li t1, 8
211+
j FN_WriteA0_common
212+
213+
FN_WriteA0_64:
214+
// reverse register when xlen is 64
215+
li t1, 16
216+
10000: slli t2, t2, 4
217+
andi a0, t0, 0xf
218+
srli t0, t0, 4
219+
or t2, t2, a0
220+
addi t1, t1, -1
221+
bnez t1, 10000b
222+
li t1, 16
223+
224+
FN_WriteA0_common:
225+
// write reversed characters
226+
li t0, 10
227+
10000: andi a0, t2, 0xf
228+
blt a0, t0, 10001f
229+
addi a0, a0, 'a'-10
230+
j 10002f
231+
10001: addi a0, a0, '0'
232+
10002: LOCAL_IO_PUTC(a0)
233+
srli t2, t2, 4
234+
addi t1, t1, -1
235+
bnez t1, 10000b
236+
ret
237+
238+
#endif // RVTEST_IO_QUIET
239+
240+
#endif // _COMPLIANCE_IO_H

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