Merge branch 'master' into master

Author: eriktai

.clang-format

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+BasedOnStyle: Chromium
+Language: Cpp
+MaxEmptyLinesToKeep: 3
+IndentCaseLabels: false
+AllowShortIfStatementsOnASingleLine: false
+AllowShortCaseLabelsOnASingleLine: false
+AllowShortLoopsOnASingleLine: false
+DerivePointerAlignment: false
+PointerAlignment: Right
+SpaceAfterCStyleCast: true
+TabWidth: 4
+UseTab: Never
+IndentWidth: 4
+BreakBeforeBraces: Linux
+AccessModifierOffset: -4

AUTHORS

@@ -1,3 +1,6 @@
+rv32emu is maintained by National Cheng Kung University, based on the
+following efforts:
+
 Fabrice Bellard - original code of RISC-V emulator:
 https://bellard.org/tinyemu/
 

LICENSE

@@ -1,5 +1,6 @@
-Original MIT License:
-
+Copyright (c) 2019 National Cheng Kung University, Taiwan
+Copyright (c) 2018 Alexander Shabarshin
+Copyright (c) 2018 Frank Buss
 Copyright (c) 2016-2017 Fabrice Bellard
 
 Permission is hereby granted, free of charge, to any person obtaining a copy

README.md

@@ -1,7 +1,7 @@
 # RISC-V RV32I[MAC] emulator with ELF support
 
-Emulator was originally created by Fabrice Bellard and then modified and shared on Hackaday by Frank Buss
-as a single C-file. Shaos added some additional statistics and macros.
+This is a RISC-V emulator for the RV32I architecture, based on [TinyEMU](https://bellard.org/tinyemu/)
+and stripped down for RV32I only.
 
 Requires libelf-dev:
 ```shell
@@ -19,8 +19,13 @@ $ make emu-rv32i
 
 Passed RV32I compliance tests from https://github.com/riscv/riscv-compliance
 - Must install the [risc-v toolchain](https://xpack.github.io/riscv-none-embed-gcc/)
+
+Run RV32I compliance tests.
+Assume `emu-rv32i` in `$PATH` environment variable.
 ```shell
-$ make RISCV_TARGET=spike RISCV_DEVICE=rv32i TARGET_SIM=/full/path/emulator variant
+$ git clone https://github.com/riscv/riscv-compliance
+$ cd riscv-compliance
+$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32i TARGET_SIM=emu-rv32i variant
 ```
 
 Compiling and running simple code:
@@ -36,15 +41,14 @@ Hello RISC-V!
 
 - RV32M and RV32A instructions may be enabled by commenting `#define STRICT_RV32I`.
 
-
 Passed RV32C compliance tests from https://github.com/riscv/riscv-compliance
 ```shell
 make C-ADDI.log
 ```
 If there is no accident, it will output the `TEST PASSED`
 
 
-- RV32C instructions can be enabled by commenting `#define RV32C`
+- RV32C instructions can be enabled by uncommenting `#define RV32C`
 ## How to build RISC-V toolchain from scratch
 
 https://github.com/riscv/riscv-gnu-toolchain