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Rename I-cache related definitions
Adjust instruction cache related defines and identifiers: - Rename IC/ic prefix to ICACHE/icache - Rename VC/vc prefix to VCACHE/vcache
1 parent 7796041 commit 724d8df

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2 files changed

+22
-22
lines changed

2 files changed

+22
-22
lines changed

riscv.c

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -181,9 +181,9 @@ static inline uint32_t read_rs2(const hart_t *vm, uint32_t insn)
181181
return vm->x_regs[decode_rs2(insn)];
182182
}
183183

184-
static inline void ic_invalidate_all(hart_t *vm)
184+
static inline void icache_invalidate_all(hart_t *vm)
185185
{
186-
memset(&vm->ic, 0, sizeof(vm->ic));
186+
memset(&vm->icache, 0, sizeof(vm->icache));
187187
}
188188

189189
/* virtual addressing */
@@ -204,7 +204,7 @@ void mmu_invalidate(hart_t *vm)
204204
vm->cache_store[set].ways[way].n_pages = 0xFFFFFFFF;
205205
vm->cache_store[set].lru = 0; /* Reset LRU to way 0 */
206206
}
207-
ic_invalidate_all(vm);
207+
icache_invalidate_all(vm);
208208
}
209209

210210
/* Pre-verify the root page table to minimize page table access during
@@ -319,29 +319,29 @@ static void mmu_fence(hart_t *vm, uint32_t insn UNUSED)
319319
static void mmu_fetch(hart_t *vm, uint32_t addr, uint32_t *value)
320320
{
321321
/* cache hit */
322-
uint32_t idx = (addr >> IC_OFFSET_BITS) & IC_INDEX_MASK;
323-
uint32_t tag = addr >> (IC_OFFSET_BITS + IC_INDEX_BITS);
324-
icache_block_t *blk = &vm->ic.i_block[idx];
322+
uint32_t idx = (addr >> ICACHE_OFFSET_BITS) & ICACHE_INDEX_MASK;
323+
uint32_t tag = addr >> (ICACHE_OFFSET_BITS + ICACHE_INDEX_BITS);
324+
icache_block_t *blk = &vm->icache.i_block[idx];
325325

326326
if (likely(blk->valid && blk->tag == tag)) {
327327
#ifdef MMU_CACHE_STATS
328328
vm->cache_fetch.hits++;
329329
#endif
330-
uint32_t ofs = addr & IC_BLOCK_MASK;
330+
uint32_t ofs = addr & ICACHE_BLOCK_MASK;
331331
*value = *(const uint32_t *) (blk->base + ofs);
332332
return;
333333
}
334334

335335
/* search the victim cache */
336-
for (int i = 0; i < VC_BLOCKS; i++) {
337-
victim_cache_block_t *vblk = &vm->ic.v_block[i];
336+
for (int i = 0; i < VCACHE_BLOCKS; i++) {
337+
victim_cache_block_t *vblk = &vm->icache.v_block[i];
338338
if (vblk->valid && vblk->tag == tag) {
339339
/* victim cache hit, block swap*/
340340
icache_block_t tmp = *blk;
341341
*blk = *vblk;
342342
*vblk = tmp;
343343

344-
uint32_t ofs = addr & IC_BLOCK_MASK;
344+
uint32_t ofs = addr & ICACHE_BLOCK_MASK;
345345
*value = *(const uint32_t *) (blk->base + ofs);
346346
return;
347347
}
@@ -371,7 +371,7 @@ static void mmu_fetch(hart_t *vm, uint32_t addr, uint32_t *value)
371371
vm->cache_fetch[index].page_addr[(addr >> 2) & MASK(RV_PAGE_SHIFT - 2)];
372372

373373
/* fill into the cache */
374-
uint32_t block_off = (addr & RV_PAGE_MASK) & ~IC_BLOCK_MASK;
374+
uint32_t block_off = (addr & RV_PAGE_MASK) & ~ICACHE_BLOCK_MASK;
375375
blk->base = (const uint8_t *) vm->cache_fetch[index].page_addr + block_off;
376376
blk->tag = tag;
377377
blk->valid = true;

riscv.h

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -86,10 +86,10 @@ typedef struct __vm_internel vm_t;
8686
* x. Therefore, we use __builtin_ctz(x) (count trailing zeros) to compute these
8787
* log2 values at compile time.
8888
*/
89-
#define IC_BLOCKS_SIZE 256
90-
#define IC_BLOCKS 256
91-
#define IC_OFFSET_BITS (__builtin_ctz((IC_BLOCKS_SIZE)))
92-
#define IC_INDEX_BITS (__builtin_ctz((IC_BLOCKS)))
89+
#define ICACHE_BLOCKS_SIZE 256
90+
#define ICACHE_BLOCKS 256
91+
#define ICACHE_OFFSET_BITS (__builtin_ctz((ICACHE_BLOCKS_SIZE)))
92+
#define ICACHE_INDEX_BITS (__builtin_ctz((ICACHE_BLOCKS)))
9393

9494
/* Define the victim cache.
9595
*
@@ -98,14 +98,14 @@ typedef struct __vm_internel vm_t;
9898
* However, the number of blocks is smaller, allowing the VC to store
9999
* a few recently evicted cache lines to reduce conflict misses.
100100
*/
101-
#define VC_BLOCK_SIZE IC_BLOCKS_SIZE
102-
#define VC_BLOCKS 16
101+
#define VCACHE_BLOCK_SIZE VCACHE_BLOCKS_SIZE
102+
#define VCACHE_BLOCKS 16
103103

104104
/* For power-of-two sizes, (size - 1) sets all low bits to 1,
105105
* allowing fast extraction of an address.
106106
*/
107-
#define IC_INDEX_MASK (IC_BLOCKS - 1)
108-
#define IC_BLOCK_MASK (IC_BLOCKS_SIZE - 1)
107+
#define ICACHE_INDEX_MASK (ICACHE_BLOCKS - 1)
108+
#define ICACHE_BLOCK_MASK (ICACHE_BLOCKS_SIZE - 1)
109109
#define RV_PAGE_MASK (RV_PAGE_SIZE - 1)
110110

111111
typedef struct {
@@ -117,12 +117,12 @@ typedef struct {
117117
typedef icache_block_t victim_cache_block_t;
118118

119119
typedef struct {
120-
icache_block_t i_block[IC_BLOCKS];
121-
victim_cache_block_t v_block[VC_BLOCKS];
120+
icache_block_t i_block[ICACHE_BLOCKS];
121+
victim_cache_block_t v_block[VCACHE_BLOCKS];
122122
} icache_t;
123123

124124
struct __hart_internal {
125-
icache_t ic;
125+
icache_t icache;
126126
uint32_t x_regs[32];
127127

128128
/* LR reservation virtual address. last bit is 1 if valid */

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