soc: nordic: vpr: align ESF_SW_IRQ_SIZEOF with new exception debug

There is new exception debugging mechanism for RISCV which needs
additional data in arch_esf structure. Since VPRs need to know
size of the part stacked by sw, ESF_SW_IRQ_SIZEOF needs to be
aligned. This ensures hardware stacking works correctly.

Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>

Author: lstnl

soc/nordic/common/vpr/soc_isr_stacking.h

@@ -92,7 +92,11 @@
  * Size of the SW managed part of the ESF in case of interrupt
  *   sizeof(__padding) + ... + sizeof(soc_context)
  */
+#ifdef CONFIG_EXCEPTION_DEBUG
+#define ESF_SW_IRQ_SIZEOF (0x10 + __callee_saved_t_SIZEOF)
+#else
 #define ESF_SW_IRQ_SIZEOF (0x10)
+#endif
 
 /*
  * VPR needs aligned(8) SP when doing HW stacking, if this condition is not fulfilled it will move