Releases: PyHDI/Pyverilog
Releases · PyHDI/Pyverilog
1.3.0
30 Dec 16:32
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Update
PLY is not included. Please install PLY by pip.
Bug fix of dataflow.graphgen
Preprocessor can accept both a list of Verilog files and Python strings as input.
Test environment
macOS 10.15.7
Python 3.9.1
Icarus Verilog 11.0
Ubuntu 18.04.5
Python 3.7.7
Icarus Verilog 10.1
1.2.1
03 May 06:23
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README.rst is removed.
Casez statement is supported.
Integer variable with an initial value is supported.
Test environment
macOS 10.15.4
Python 3.7.7
Icarus Verilog 10.3
Ubuntu 18.04.4
Python 3.7.2
Icarus Verilog 10.1
1.2.0
19 Nov 10:53
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N-dimension array for input, output, inout, reg, wire, is supported.
Preprocessor supports PYVERILOG_IVERILOG variable to pass a custom iverilog command to the preprocessor.
In Preprocessor, subprocess.call() method does NOT use "shell=True" for the security issue.
Test environment
macOS 10.15.1
Python 3.7.5
Icarus Verilog 10.3
Ubuntu 18.04.3
Python 3.6.8
Icarus Verilog 10.1
1.1.4
30 Mar 15:50
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Update
Some SystemVerilog features are supported.
Test environment
Mac OSX 10.14.4
Python 3.7.2
Icarus Verilog 10.2
Ubuntu 18.04.2
Python 3.6.7
Icarus Verilog 10.1
1.1.3
25 Nov 03:33
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Update
python2 support is disabled.
uft8 is specified in setup.py
Test environment
Mac OSX 10.14
Python 3.7.1
Icarus Verilog 10.2
Ubuntu 18.04.1
Python 3.6.6
Icarus Verilog 10.1
1.1.2
01 Jul 15:04
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Update
Internally-used ply library is updated for avoiding unessential recompilation.
Test environment
Mac OSX 10.13.5
Python 3.7.0
Python 2.7.15
Icarus Verilog 10.2
Ubuntu 16.04
Python 3.5.2
Python 2.7.12
Icarus Verilog 0.9.7
1.1.1
04 Oct 14:04
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Update
Improved Verilog parser: "parameter signed" is supported.
Test environment
Mac OSX 10.12.6
Python 3.6.2
Python 2.7.10
Icarus Verilog 0.9.7
Ubuntu 16.04
Python 3.5.2
Python 2.7.12
Icarus Verilog 0.9.7
1.1.0
01 Oct 03:02
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Update
A bug of scope name parsing in the dataflow analyzer is fixed.
Test environment
Mac OSX 10.12.6
Python 3.6.2
Python 2.7.10
Icarus Verilog 0.9.7
Ubuntu 16.04
Python 3.5.2
Python 2.7.12
Icarus Verilog 0.9.7
1.0.9
02 May 15:43
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Update
New AST node "EmbeddedCode" is implemented for Veriloggen.
Test environment
Mac OSX 10.12.4
python 3.6.1
python 2.7.13
icarus verilog 0.9.7
Ubuntu 16.04
python 3.5.2
python 2.7.12
icarus verilog 0.9.7
1.0.8
10 Apr 04:17
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Update
Empty port argument in an instance creation is supported.
Email address is updated.
Test environment
Mac OSX 10.12.4
python 3.6.1
python 2.7.13
icarus verilog 0.9.7
Ubuntu 16.04
python 3.5.2
python 2.7.12
icarus verilog 0.9.7