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soc: nordic: vpr: align ESF_SW_IRQ_SIZEOF with new exception debug #98931

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soc: nordic: vpr: align ESF_SW_IRQ_SIZEOF with new exception debug #98931

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1 change: 1 addition & 0 deletions arch/riscv/core/offsets/offsets.c
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Original file line number Diff line number Diff line change
Expand Up @@ -127,6 +127,7 @@ GEN_OFFSET_STRUCT(arch_esf, soc_context);
#endif
#if defined(CONFIG_RISCV_SOC_OFFSETS)
GEN_SOC_OFFSET_SYMS();
GEN_ABSOLUTE_SYM(__struct_soc_esf_SIZEOF, sizeof(struct soc_esf));
#endif

GEN_ABSOLUTE_SYM(__struct_arch_esf_SIZEOF, sizeof(struct arch_esf));
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19 changes: 15 additions & 4 deletions soc/nordic/common/vpr/soc_isr_stacking.h
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,15 @@
#define VPR_CPU DT_INST(0, nordic_vpr)

#ifdef CONFIG_EXCEPTION_DEBUG
#define ESF_CSF _callee_saved_t *csf
/*
* Explicit padding is needed for VPRs, because they use hardware stacking on part of arch_esf and
* ESF_SW_IRQ_SIZEOF needs to be calculated accordingly.
*/

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BLOCK_COMMENT_STYLE 

soc/nordic/common/vpr/soc_isr_stacking.h:21  Block comments should align the * on each line
#define ESF_CSF \
_callee_saved_t *csf; \
unsigned long padding1; \
unsigned long padding2; \
unsigned long padding3;
#else
#define ESF_CSF
#endif /* CONFIG_EXCEPTION_DEBUG */
Expand Down Expand Up @@ -90,10 +98,13 @@

/*
* Size of the SW managed part of the ESF in case of interrupt
* sizeof(__padding) + ... + sizeof(soc_context)
* sizeof(s0) + sizeof(mstatus) + sizeof(soc_context) +...+ sizeof(ESF_CSF)
*/
#define ESF_SW_IRQ_SIZEOF (0x10)

#ifdef CONFIG_EXCEPTION_DEBUG
#define ESF_SW_IRQ_SIZEOF (0x8 + __struct_soc_esf_SIZEOF + 0x10)
#else
#define ESF_SW_IRQ_SIZEOF (0x8 + __struct_soc_esf_SIZEOF)
#endif
/*
* VPR needs aligned(8) SP when doing HW stacking, if this condition is not fulfilled it will move
* SP by additional 4 bytes when HW stacking is done. This will be indicated by LSB bit in stacked
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