soc: nordic: vpr: align ESF_SW_IRQ_SIZEOF with new exception debug #98931
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This was referenced Nov 5, 2025
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I need to review the fix, sorry that is why I added DNM for now. |
… used There is new exception debugging mechanism for RISC-V which needs additional member in arch_esf structure. VPRs handle stacking partially in hw so exact position of some stack members needs to be at the end of arch_esf, so explicit padding is needed. Aligned also ESF_SW_IRQ_SIZEOF when exception debug is used. Added generation of __struct_soc_esf_SIZEOF which helps when calculating offsets. Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
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There is new exception debugging mechanism for RISCV which needs additional data in arch_esf structure. Since VPRs need to know size of the part stacked by sw, ESF_SW_IRQ_SIZEOF needs to be aligned. This ensures hardware stacking works correctly.
Fixes #98422